< BK21+ BEST Seminar Series Announcement> 

Time and Date : 11:00 ~ 12:00 Thursday 05/16/2019

Place : C616, Engineering Building #3

Title : Tackling the end of scaling in semiconductors through new technologies: 3-dimensional integrated circuits and gate-all-around FETs
Abstract:
The industry is worrying that the everlasting trend of Moore’s law in transistor scaling is “finally” reaching to an end in a very near future. This unfortunate forecast is asking the industry to devise a reasonable breakthrough so that the continued improvement in semiconductor systems could continue its momentum despite the unwanted news we are facing these days. In this talk, we will discuss some promising technologies that are considered as a breakthrough to the anticipation of “end of scaling.” 3-dimensional integrated circuits (3D ICs) is a technology that stacks dies on the top of each other by using vertical interconnect technology such as through-silicon vias (TSVs) and monolithic inter-tier vias (MIVs). In this talk, we will discuss one important theme in 3D ICs that is very critical to IC design: low-power 3D ICs. Another key technology that is considered as a breakthrough is a new device technology called gate-all-around FETs. We will discuss what are the impacts the VLSI industry when these new devices are introduced to designs.

Presenter: Daegun Cho, Assistant Professor / School of Electronics Engineering college of IT Engineering, Kyungpook National University

Host: Prof. Kang, Sungho, Yonsei EEE