| 2024-01 |
Ferroelectric FET Nonvolatile Sense-Amplifier-Based Flip-Flops for Low Voltage Operation |
IEEE Transactions on Circuits and Systems I: Regular Papers
|
| 2023-11 |
An Energy-Efficient Design of TSV I/O for HBM With a Data Rate up to 10 Gb/s |
IEEE Journal of Solid-State Circuits
|
| 2023-09 |
An Offset-Canceled Sense Amplifier for DRAMs With Hidden Offset-Cancellation Time and Boosted Internal-Voltage-Difference |
IEEE Transactions on Circuits and Systems II: Express Briefs
|
| 2023-08 |
Design consideration of ferroelectric field-effect-transistors with metal–ferroelectric–metal capacitor for ternary content addressable memory |
Solid-State Electronics
|
| 2023-07 |
Dual-Mode Operations of Self-Rectifying Ferroelectric Tunnel Junction Crosspoint Array for High-Density Integration of IoT Devices |
IEEE Journal of Solid-State Circuits
|
| 2023-07 |
High-Precision and Low-Power Offset Canceling Tri-State Sensing Latch in NAND Flash Memory |
IEEE Transactions on Circuits and Systems II: Express Briefs
|
| 2023-06 |
A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC |
Digest of Technical Papers - Symposium on VLSI Technology
|
| 2023-06 |
A Static Contention-Free Dual-Edge-Triggered Flip-Flop with Redundant Internal Node Transition Elimination for Ultra-Low-Power Applications |
Digest of Technical Papers - Symposium on VLSI Technology
|
| 2023-02 |
Cross-Coupled Ferroelectric FET-Based Ternary Content Addressable Memory With Energy-Efficient Match Line Scheme |
IEEE Transactions on Circuits and Systems I: Regular Papers
|
| 2023-01 |
Power-Delay Area-Efficient Processing-In-Memory Based on Nanocrystalline Hafnia Ferroelectric Field-Effect Transistors |
ACS Applied Materials & Interfaces
|
| 2023-01 |
Effect of Floating Gate Insertion on the Analog States of Ferroelectric Field-Effect Transistors |
IEEE TRANSACTIONS ON ELECTRON DEVICES
|
| 2023-01 |
Local Bit-Line SRAM Architecture With Data-Aware Power-Gating Write Assist |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
|
| 2022-07 |
Non-Volatile Majority Function Logic using Ferroelectric Memory for Logic in Memory Technology |
IEEE ELECTRON DEVICE LETTERS
|
| 2022-06 |
A Low Power TSV I/O with Data Rate up to 10 Gb/s for Next Generation HBM |
Digest of Technical Papers - Symposium on VLSI Technology
|
| 2022-06 |
A 14-nm Low Voltage SRAM with Charge-Recycling and Charge Self-Saving Techniques for Low-Power Applications |
Digest of Technical Papers - Symposium on VLSI Technology
|
| 2022-06 |
A 5 Gb/s Time-Interleaved Voltage-Mode Duobinary Encoding Scheme for 3-D-Stacked IC |
IEEE JOURNAL OF SOLID-STATE CIRCUITS
|
| 2022-04 |
A Sneak Current Compensation Scheme With Offset Cancellation Sensing Circuit for ReRAM-Based Cross-Point Memory Array |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
|
| 2022-04 |
SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased With Technology Scaling |
IEEE JOURNAL OF SOLID-STATE CIRCUITS
|
| 2022-03 |
SRAM Write Assist Circuit Using Cell Supply Voltage Self-Collapse With Bitline Charge Sharing for Near-Threshold Operation |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
|
| 2021-12 |
High Performance and Self-rectifying Hafnia-based Ferroelectric Tunnel Junction for Neuromorphic Computing and TCAM Applications |
Technical Digest - International Electron Devices Meeting, IEDM
|
| 2021-10 |
Highly Accurate, Fully Digital Temperature Sensor With Curvature Correction |
IEEE SENSORS JOURNAL
|
| 2021-09 |
Comparative Analysis and Energy-Efficient Write Scheme of Ferroelectric FET-Based Memory Cells |
IEEE Access
|
| 2021-06 |
A 0.166 pJ/b/pF, 3.5–5 Gb/s TSV I/O Interface With VOH Drift Control |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
|
| 2021-06 |
Imbalance-Tolerant Bit-Line Sense Amplifier for Dummy-Less Open Bit-Line Scheme in DRAM |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
|
| 2021-06 |
Self-Referenced Single-Ended Resistance Monitoring Write Termination Scheme for STT-RAM Write Energy Reduction |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
|
| 2021-06 |
Bitline Charge Sharing Suppressed Bitline and Cell Supply Collapse Assists for Energy-Efficient 6T SRAM |
IEEE Access
|
| 2021-04 |
Differential Read/Write 7T SRAM With Bit-Interleaved Structure for Near-Threshold Operation |
IEEE Access
|
| 2021-04 |
Adaptive Sensing Voltage Modulation Technique in Cross-Point OTS-PRAM |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2021-04 |
A 6.9-μm2 3.26-ns 31.25-fj Robust Level Shifter With Wide Voltage and Frequency Ranges |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
|
| 2021-03 |
Environmental-Variation-Tolerant Magnetic Tunnel Junction-Based Physical Unclonable Function Cell With Auto Write-Back Technique |
IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY
|
| 2021-02 |
High-Performance and Area-Efficient Ferroelectric FET-Based Nonvolatile Flip-Flops |
IEEE Access
|
| 2021-02 |
A Wide-Range Static Current-Free Current Mirror-Based LS With Logic Error Detection for Near-Threshold Operation |
IEEE JOURNAL OF SOLID-STATE CIRCUITS
|
| 2021-02 |
All-Bit-Line Read Scheme With Locking Bit-Line and Amplifying Sense Node in NAND Flash |
IEEE Access
|
| 2021-01 |
STT-MRAM Sensing: A Review |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
|
| 2020-12 |
A Novel Matchline Scheduling Method for Low-Power and Reliable Search Operation in Cross-Point-Array Nonvolatile Ternary CAM |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2020-12 |
Area- and Energy-Efficient STDP Learning Algorithm for Spiking Neural Network SoC |
IEEE Access
|
| 2020-10 |
An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache |
IEEE Access
|
| 2020-10 |
CNN Acceleration With Hardware-Efficient Dataflow for Super-Resolution |
IEEE Access
|
| 2020-05 |
One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
|
| 2020-04 |
PMOS Pass Gate Local Bitline SRAM Architecture with Virtual V_{\mathrm{SS}} for Near-Threshold Operation |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2020-03 |
Highly Independent MTJ-Based PUF System Using Diode-Connected Transistor and Two-Step Postprocessing for Improved Response Stability |
IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY
|
| 2020-01 |
Current Measurement Transducer Based on Current-To-Voltage-To-Frequency Converting Ring Oscillator with Cascade Bias Circuit |
SENSORS
|
| 2019-11 |
Offset-Canceling Single-Ended Sensing Scheme With One-Bit-Line Precharge Architecture for Resistive Nonvolatile Memory in 65-nm CMOS |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2019-10 |
Sensing Margin Enhancement Technique Utilizing Boosted Reference Voltage for Low-Voltage and High-Density DRAM |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2019-08 |
Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time |
IEEE JOURNAL OF SOLID-STATE CIRCUITS
|
| 2019-08 |
Variation-Tolerant WL Driving Scheme for High-Capacity NAND Flash Memory |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2019-08 |
Offset-Cancellation Sensing-Circuit-Based Nonvolatile Flip-Flop Operating in Near-Threshold Voltage Region |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
|
| 2019-04 |
Thermoelectric cooling read for resolving read disturb with inrush current issue in OTS-PRAM |
IEEE TRANSACTIONS ON NANOTECHNOLOGY
|
| 2019-03 |
Bitline Charge-Recycling SRAM Write Assist Circuitry for V-MIN Improvement and Energy Saving |
IEEE JOURNAL OF SOLID-STATE CIRCUITS
|
| 2019-02 |
A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2019-01 |
Parasitic RC Aware Delay Corner Model for Sub-10-nm Logic Circuit Design |
IEEE TRANSACTIONS ON ELECTRON DEVICES
|
| 2018-06 |
0.293-mm(2) Fast Transient Response Hysteretic Quasi-V-2 DC-DC Converter With Area-Efficient Time-Domain-Based Controller in 0.35-mu m CMOS |
IEEE JOURNAL OF SOLID-STATE CIRCUITS
|
| 2018-06 |
All-Digital Process-Variation-Calibrated Timing Generator for ATE With 1.95-ps Resolution and Maximum 1.2-GHz Test Rate |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2018-04 |
Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2018-01 |
Data-Cell-Variation-Tolerant Dual-Mode Sensing Scheme for Deep Submicrometer STT-RAM |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
|
| 2017-12 |
GRO-TDC with gate-switch-based delay cell halving resolution limit |
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
|
| 2017-10 |
Pre-Charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
|
| 2017-08 |
SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
|
| 2017-06 |
Incremental Bitline Voltage Sensing Scheme With Half-Adaptive Threshold Reference Scheme in MLC PRAM |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
|
| 2017-06 |
A 10T-4MTJ Nonvolatile Ternary CAM Cell for Reliable Search Operation and a Compact Area |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
|
| 2017-03 |
Power-Gated 9T SRAM Cell for Low-Energy Operation |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2017-02 |
Offset-Canceling Current-Sampling Sense Amplifier for Resistive Nonvolatile Memory in 65 nm CMOS |
IEEE JOURNAL OF SOLID-STATE CIRCUITS
|
| 2016-12 |
저 손실 열전변환 하베스팅을 위해 제로전류센서의 오프셋을 조절하는 부스트 컨버터 |
전기전자학회논문지
|
| 2016-11 |
Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
|
| 2016-11 |
All-Digital ON-Chip Process Sensor Using Ratioed Inverter-Based Ring Oscillator |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2016-10 |
Transient Cell Supply Voltage Collapse Write Assist Using Charge Redistribution |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
|
| 2016-09 |
Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2016-09 |
Corner-Aware Dynamic Gate Voltage Scheme to Achieve High Read Yield in STT-RAM |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2016-07 |
Single Bit-line 7T SRAM Cell for Near-threshold Voltage Operation with Enhanced Performance and Energy in 14 nm FinFET Technology |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
|
| 2016-06 |
비트라인 트래킹을 위한 replica 기술에 관한 연구 |
전기전자학회논문지
|
| 2016-06 |
Read Disturbance Reduction Technique for Offset-Canceling Dual-Stage Sensing Circuits in Deep Submicronmeter STT-RAM |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
|
| 2016-04 |
Thermal and solar energy harvesting boost converter with time-multiplexing MPPT algorithm |
IEICE ELECTRONICS EXPRESS
|
| 2016-04 |
High-speed, Low-power, and Highly Reliable Frequency Multiplier for DLL-based Clock Generator |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2016-04 |
An Offset-Tolerant Dual-Reference-Voltage Sensing Scheme for Deep Submicrometer STT-RAM |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2016-04 |
Full-Swing Local Bit-Line SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2016-03 |
All-Digital 90° Phase-Shift DLL with Dithering Jitter Suppression Scheme |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2015-12 |
Low power SRAM design for 14nm GAA Si-Nanowire technology |
MICROELECTRONICS JOURNAL
|
| 2015-12 |
A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
|
| 2015-11 |
All-Digital Fast-Locking Delay-Locked Loop Using Cyclic-Locking Loop for DRAM |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
|
| 2015-11 |
Single-ended 9T SRAM Cell for Near-threshold Voltage Operation with Enhanced Read Performance in 22-nm FinFET Technology |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2015-08 |
An Energy-Efficient All-Digital Time-Domain-Based CMO Temperature Sensor for SoC Thermal Management |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2015-08 |
Temperature-Tracking Sensing Scheme With Adaptive Precharge and Noise Compensation Scheme in PRAM |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
|
| 2015-07 |
Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2015-07 |
Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
|
| 2015-06 |
SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
|
| 2015-06 |
Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
|
| 2015-06 |
Variation-Aware Figure of Merit for Integrated Circuit in Near-Threshold Region |
IEEE TRANSACTIONS ON ELECTRON DEVICES
|
| 2015-06 |
Design of a 22-nm FinFET-Based SRAM with Read Buffer for Near-Threshold Voltage Operation |
IEEE TRANSACTIONS ON ELECTRON DEVICES
|
| 2015-04 |
Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
|
| 2015-04 |
Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2015-03 |
Level-Converting Retention Flip-Flop for Reducing Stanby Power in ZigBee SoCs |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2014-12 |
Reference-Scheme Study and Novel Reference Scheme for Deep Submicrometer STT-RAM |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
|