| 2014-07 |
An Offset-Canceling Triple-Stage Sensing Circuit for Deep Submicrometer STT-RAM |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2014-07 |
STT-MRAM Sensing Circuit With Self-Body Biasing in Deep Submicron Technologies |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2014-06 |
One-Sided Static Noise Margin and Gaussian-Tail-Fitting Method for SRAM |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2014-04 |
An MTJ-based non-volatile flip-flop for high-performance SoC |
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
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| 2014-03 |
A Split-Path Sensing Circuit for Spin Torque Transfer MRAM |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
|
| 2014-02 |
Comparative Study of Various Latch-Type Sense Amplifiers |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2014-01 |
An Energy Efficient Time-Domain Temperature Sensor for Low-Power On-Chip Thermal Management |
IEEE SENSORS JOURNAL
|
| 2014-01 |
Process-Variation-Calibrated Multiphase Delay Locked Loop With a Loop-Embedded Duty Cycle Corrector |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
|
| 2013-07 |
Dynamic mixed serial-parallel content addressable memory (DMSP CAM) |
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
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| 2013-07 |
ADDLL for Clock-Deskew Buffer in High-Performance SoCs |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2012-11 |
A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2012-10 |
Process Variation Tolerant All-Digital 90 degrees Phase Shift DLL for DDR3 Interface |
IEEE Transactions on Circuits and Systems I-Regular Papers
|
| 2012-10 |
Read-Preferred SRAM Cell With Write-Assist Circuit Using Back-Gate ETSOI Transistors in 22-nm Technology |
IEEE TRANSACTIONS ON ELECTRON DEVICES
|
| 2012-09 |
A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator |
IEEE Transactions on Circuits and Systems I-Regular Papers
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| 2012-01 |
A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM) |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2011-09 |
Asymmetric Independent-Gate MOSFET SRAM for High Stability |
IEEE TRANSACTIONS ON ELECTRON DEVICES
|
| 2011-03 |
Sensing margin trend with technology scaling in MRAM |
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
|
| 2011-03 |
Effects of Electrical Characteristics on the Non-Rectangular Gate Structure Variations for the Multifinger MOSFETs |
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY
|
| 2010-11 |
A 90 phase-shift DLL with closed-loop DCC for high-speed mobile DRAM interface |
IEEE Transactions on Consumer Electronics
|
| 2010-11 |
FinFET SRAM Optimization With Fin Thickness and Surface Orientation |
IEEE Transactions on Electron Devices
|
| 2010-11 |
Offset voltage estimation model for latch-type sense amplifiers |
Iet Circuits Devices & Systems
|
| 2010-08 |
A DLL Based Clock Generator for Low-Power Mobile SoCs |
IEEE Transactions on Consumer Electronics
|
| 2010-06 |
Design Methodologies for STT-MRAM (Spin-Torque Transfer Magnetic Random Access Memory) Sensing Circuits |
IEICE TRANSACTIONS ON ELECTRONICS
|
| 2009-07 |
Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
|
| 2009-01 |
Serial-Parallel Content Addressable Memory with a Conditional Driver (SPCwCD) |
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
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| 2008-09 |
Numerical estimation of yield in sub-100-nm SRAM design using Monte Carlo simulation |
IEEE Transactions on Circuits and Systems II-Express Briefs
|
| 2008-03 |
Race-free mixed serial-parallel comparison for low power content addressable memory |
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
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| 2007-08 |
Statistical simulation methodology for sub-100nm memory design |
ELECTRONICS LETTERS
|
| 2005-08 |
A 32-bit carry lookahead adder using dual-path all-N logic |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2003-10 |
Coupling delay optimization by Temporal Decorrelation using Dual Threshold Voltage Technique |
Transactions on VLSI
|
| 2003-04 |
minimum Delay Optimization for Domino Logic circuits a coupling-Awavw approach |
Transactions on Design Automation of Electronic Systems
|
| 2003-02 |
Noise-Awave Interconnect Power Optimization in Domino Logic Synthesis |
Transaction on VLSI
|
| 2003-01 |
Timing Constraints for Domino Logic gates with Timing Dependent Keepers |
Transactions on CAD of IC &Systems
|
| 2002-10 |
noise Constrained Transistor Sizing and Power Optimization for Dual Vt Domino Logic |
Transactions on VLSI
|
| 2002-08 |
High performance dynamic logic Incorporating Gate Voltage |
Electrics Letters
|
| 2002-06 |
High speed CMOS circuits with parallel Dynamic Logic and Speed-enhanced skewed static logic |
Transactions on circuits and Systems part II : analog and digital signal processing
|
| 2001-06 |
Coupling-Awave Minimum Delay Optimization for Domino Logic Circuits |
ELECTRONICS LETTERS
|
| 2000-03 |
Modular Charge Recycling Pass Transistor Logic(MCRPL) |
ELECTRONICS LETTERS
|